_florent_: I was able to finally get working serial port output. Idk what I was doing wrong this whole time, but its whatever now lol
important thing is it's now fixed and I have a "known-to-work" base
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mithro: I did a post-synthesis simulation of tinyfpga; incredibly, it matches pre-synthesis simulation. Meaning I guess the bug appears during par or later. This is a nasty bug
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Actually no I lied... post-synthesis doesn't match, but it doesn't fail where I expect it to