#timvideos

mithro: I've had no Internet for about the past week, but hope to get somewhere by the end of the week

CarlFK: they are called system facts. A full list is here: http://docs.ansible.com/ansible/playbooks_varia...

Title: Variables Ansible Documentation (at docs.ansible.com)

paddatrapper: thanks - knowing the right terms helps

tumbleweed: Ping me when you are in Hamburg :-)

mithro: ack. I land at 3

tumbleweed: Where are you staying?

mithro: an airbnb, fairly near by

I'm at the Marriott

ok, I think that's in the opposite direction, but still pretty close

cr1901_modern: ping?

mithro: pong

cr1901_modern: How's things going?

mithro: I'm kinda stuck. I'm reflashing the scope firmware and I'll play with an IPython notebook.

I've been thinking about if having gdb support would help

mithro: It may very well help, but something else is bothering me

mithro: LM32 has a cache. It should be caching everything read from flash

Why would a value read from cache be different when its read a second time?

cr1901_modern: no idea

mithro: Is the ROM section uncached?

cr1901_modern: NFI....

I may need to simulate parts of the CPU in iverilog.

cr1901_modern: https://github.com/enjoy-digital/litex/pull/14

Title: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at github.com)

cr1901_modern: There is a "sim" target which uses verilator

mithro: Re: that pull request... I'm not sure it works. For 1-bit width, I think the MiSoC fix doesn't send the data down miso

cr1901_modern: Can you put a comment on it

mithro: Done. (Albiet poorly formatted)

cr1901_modern: what's your problem with lm32 exactly ?

[mithro/HDMI2USB-litex-firmware/nextgen#60] (d801073): The build passed. (https://travis-ci.org/mithro/HDMI2USB-litex-fir...)

ysionneau: He is trying to get the bios to boot from spi flash directly

_florent_: ping?

_florent_: Currently got access to a NeTV2 board and trying to get the BaseSoC to boot

mithro: is he sure that what he reads from flash is correct first?

he can try booting a small BIOS from blockram and then do mr to read the flash from the bios cmd line

ysionneau: We just use the wishbone uart bridge to read the spi flash

ysionneau: That was returning the contents expected

hmmm ok, weird

is the code on some github branch?

ysionneau: I can forward what I sent cr1901

mithro: yep I can have a look :)

ysionneau: email sent

got it thx !

ysionneau: Oh and https://github.com/enjoy-digital/litex/pull/14/...

Title: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at github.com)

Why would a value read from cache be different .... Can the cache be disabled to see if that fixes things? (hoping this is easy to try and easy to see results)