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4:31 AM
tumbleweed
mithro: so now, I have a logic analyzer. But I don't know what I'm doing with it
4:31 AM
and can't find the UART on the TOFE pinout in the opsis docs
4:37 AM
mithro
tumbleweed: You want to attach the logic analyzer to the I2C bus and reset line between FX2 and the FPGA
4:39 AM
tumbleweed: one problem you have is that the I2C CLK isn't on a header anywhere
4:42 AM
tumbleweed
I'll need some help finding it
4:51 AM
mithro
UMAC1 is probably the best IC to use
4:52 AM
4:52 AM
tpb
Title: HDMI2USB-numato-opsis-hardware/Numato-Opsis-v3-prod-3-g83e7bd5.pdf at master · timvideos/HDMI2USB-numato-opsis-hardware · GitHub (at
github.com )
4:54 AM
tumbleweed
U23 is nice and big, so I'm giving it a shot
4:56 AM
mithro
tumbleweed: yeah
4:56 AM
SDA signal is also avaliable on P18
4:57 AM
The reset signal is available on K3 == JFX2-RST
5:03 AM
tumbleweed
yeah
5:03 AM
trying to figure out how external clock is supposed to work
5:07 AM
mithro
tumbleweed: hrm?
5:10 AM
tumbleweed
how do I get it to use the I2C bus' clock?
5:13 AM
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5:14 AM
mithro
tumbleweed: You just want to capture the clock + data signals?
5:15 AM
tumbleweed
presumably
5:23 AM
mithro
tumbleweed: So you need to attach your logic analyzer to pins 5 and 6 of UMAC1
5:26 AM
tumbleweed
yeah, I gave up on external clock, and just captured at a higher clock rate
5:26 AM
I have some analysis which is basically a screen full of bus errors
5:26 AM
mithro
tumbleweed: oh, yeah you definitely want to oversample it
5:26 AM
tumbleweed: you also want to trigger on the JFX2-RST
5:27 AM
tumbleweed
aha, let's try that
5:29 AM
JFX2-RST seems to stay high a lot
5:30 AM
mithro
tumbleweed: That is expected, the FX2 is only running when it is high IIRC
5:30 AM
you pull it low to reset the FX2
5:30 AM
tumbleweed
that's annoying for triggering
5:31 AM
mithro
tumbleweed: you want to trigger on it going high
5:31 AM
tumbleweed: the SDA and SCL should be idle for the rest of the time
5:32 AM
tumbleweed: but just after a reset it will read a bunch of stuff out of the EEPROM first, and then from the FPGA second
5:37 AM
tumbleweed was getting data before, now all the pins just seem to be high :/
5:37 AM
tumbleweed: The data will only occur after a reset
5:42 AM
ssk1328: ping?
5:51 AM
tumbleweed
mithro: no, I mean, the clock line is just staying high now
5:51 AM
tumbleweed is confused
5:52 AM
mithro
tumbleweed: the clock line will only toggle when it is sending data
5:52 AM
tumbleweed: Do you know how I2C works?
5:52 AM
tumbleweed
well it's serial, so yes, that's what I'd expect
5:52 AM
but that's not what's happening
5:52 AM
which is why I'm confused
5:53 AM
I don't know the I2C protocol
5:53 AM
but I do know that these logic lines probably shouldn't be staying high
5:56 AM
aha, because I'm being a numpty
5:56 AM
well that was obvious
5:56 AM
but you know...
6:01 AM
mithro
tumbleweed: When idle, they will remain high
6:02 AM
6:02 AM
tpb
6:02 AM
tumbleweed
no, there seems to be a bug in this software
6:03 AM
if you use too big a capture buffer, it's all corrupted
6:03 AM
I noticed this earlier
6:05 AM
ssk1328
mithro: Pong
6:05 AM
mithro: did you see the doc I sent here
6:05 AM
mithro
ssk1328: yes
6:05 AM
ssk1328: I don't quite understand the first section
6:06 AM
ssk1328
mithro: that's a problem I am unable to solve
6:07 AM
mithro
ssk1328: You can have multiple sinks in a component
6:07 AM
ssk1328: Why doesn't the adder block just have two sinks?
6:07 AM
ssk1328
I tried that
6:07 AM
mithro: That gave a error
6:07 AM
Maybe not using the correct way
6:08 AM
mithro
ssk1328: What was the error?
6:08 AM
tumbleweed
6:09 AM
ssk1328
mithro: Let me reproduce, but it was something about Endpoint can't have two definition of sink
6:10 AM
tumbleweed
6:11 AM
mithro
tumbleweed: Okay, lets start with FX2-RST - the correct behaviour is that on boot it goes high, then at some point later it will get pulled low for a period and then go high again
6:11 AM
tumbleweed
it is rather wobbly
6:12 AM
it's line 2 in my capture
6:12 AM
mithro
tumbleweed: That is the FPGA resetting the FX2 to get it to read the new firmware
6:12 AM
I dunno how to read a sla file?
6:12 AM
ssk1328: Can you give me edit access so I can play with your block diagram?
6:12 AM
tumbleweed
mithro: with SUMP
6:13 AM
mithro: at 1.8ms, it seems to settle down
6:14 AM
ssk1328
mithro: Sharing setting changed
6:16 AM
mithro
6:16 AM
tpb
Title: HDMI2USB-misoc-firmware/fx2.c at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at
github.com )
6:17 AM
tumbleweed
when I say wobbly I mean it's toggling faster than the I2C clock, at times
6:17 AM
mithro
6:17 AM
tpb
Title: HDMI2USB-misoc-firmware/opsis.py at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at
github.com )
6:18 AM
mithro
tumbleweed: It shouldn't be toggling....
6:18 AM
tumbleweed
well yeah, that's why I mention it
6:22 AM
ssk1328
mithro: This is how am I doing it right now, and surprisingly no errors turned up
6:22 AM
6:22 AM
tpb
6:23 AM
ssk1328
mithro: I have started the make gateware for this, lets how this works out
6:28 AM
mithro: Made a typo in above code
6:28 AM
mithro: I am gonna pastebin the error I got here
6:29 AM
6:29 AM
tpb
6:31 AM
ssk1328
6:31 AM
tpb
6:31 AM
mithro
ssk1328: That isn't an error?
6:33 AM
ssk1328
mithro: The second pastebin is the terminal output of error I get
6:33 AM
tumbleweed
mithro: I'm guessing it could just be a very slow transition from low to high
6:34 AM
but there are still some spikes to low
6:34 AM
nafc
6:38 AM
mithro
ssk1328: Ask _florent_ or in #m-labs
6:38 AM
ssk1328
mithro: Okay
7:00 AM
mithro
tumbleweed: It's hard for me to tell if the problem is actually your FX2 line or your equipment?
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10:12 AM
ssk1328: I updated your document with my thinking about the pipeline
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tumbleweed
mithro: I can't tell, either
16:19 PM
mithro: and it's not necessarily a problem. How did the rest of that I2C dump look?
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ssk1328
mithro: I saw the changes