Title: HDMI2USB-misoc-firmware/README.md at or1k · mithro/HDMI2USB-misoc-firmware · GitHub (at github.com)
mithro
BRB for the GSoC meeting
shenki
see you there
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+ sudo adduser root dialout
The user `root' is already a member of `dialout'.
thats wrong
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rohitksingh
hello! turns out the all 3 independent internet lines at Numato office have died today. I'm on from mobile hotspot, so please excuse (dis)connection issues.
anyone present on VC?
mithro
Okay, here now
xfxf
rohitksingh: hi! i'm trying to connect in
mithro
I wasn't planning on doing a VC
rohitksingh
xfxf: hi! :)
ohh
good then
xfxf
oh right
just here?
_florent_
hi
xfxf
hi!
rohitksingh
_florent_ hi!
xfxf
aw man you don't get to see my ridiculously stupid big blue gamer headset
rohitksingh
hehe :D
shenki
oh, right. ive been rushing around getting a laptop to do a vc :)
tija
Hello everyone!
rohitksingh
shenki: same here...I freaked out after knowing that all net lines were down
shenki
hey tija
rohitksingh: :)
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booted the kernel in the sim
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mithro
_florent_: What frequency is the SDRAM on the Atlys suppose to be running at? 300MHz with sysclk of 75MHz?
I feel deja vu with that question :P
_florent_
mithro: yes 300Mhz on Atlys (1:2 phy), 400MHz on Opsis (1:4 phy)
mithro
_florent_: Great! I added some asserts which checked the PLL was generating the right speed clock signals and found out a bunch of my comments were wrong
_florent_
ok good
shenki
place and route is taking forever :/
mithro
shenki: are you targetting the HDMI2USB target?
shenki: use the base target, it takes like 5 minutes
shenki: you probably want to target the Opsis as well, I think I still have your Atlys, right?
_florent_: btw, what are your plans around merging the stuff in the opsis_soc into the HDMI2USB firmware?
shenki: export BOARD=opsis; export TARGET=base
_florent_
mithro: I'd like to get things working on the opsis_soc and then merge everything that is needed
hdmi_in was easy to convert
hdmi_out need to be refactored if we want to avoid using DataflowGraph that was removed from Migen
jpeg encoder will be easy to re-integrate
shenki
mithro: oh, ok. should have asked about that a few hours ago :)
Intermediate status: 1679 unrouted; REAL time: 1 hrs 2 mins 16 secs
still going
mithro: i should kill it?
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mithro: im doing all this work on my novena. i should add a target for that
_florent_
shenki: you are using hdmi2usb on the novena FPGA?
shenki
_florent_: no, i haven't touched the fpga yet
_florent_: im just using it as a very expensive console :)
_florent_
ah ok... :), at least if you want to try, it should use the same DDR3 memory
shenki
oh cool
_florent_: do you have one?
_florent_
yes, but I haven't done too much things with it for now
mithro
Even the video VideoMixerSoC is much faster than the full HDMI2USB SoC - it seems the JPEG encoder makes things crappy - hence the rewrite :)
_florent_: BTW Do you think that moving the firmware into the SPI flash would change the PAR at all? I was thinking that it would just end up freeing block RAM?
_florent_: at some point you'll need to do a liteAXI so that we can interface a hard core to the FPGA on the Novena and Zynq ICs
_florent_
maybe. If you want you can test by removing the firmware ram, it will not be fonctionnal, but we will have an idea if it eases things
mithro
_florent_: fixing these timing constraints seem to make the long compile time happen less often too
_florent_
we already have stream interface that are very close to AXI in misoc
AXI is just some stream interfaces coupled togethers
mithro
I believe the ARM and FPGA on the Novena are set up for AXI?